1. Field of the Invention
The present invention relates to a semiconductor storage device, and, more particular, is suitably applied to a method of realizing a reduction in power consumption of an SRAM by using power supplies that generate a plurality of voltages.
2. Description of the Related Art
According to the progress in reduction of power consumption of system LSIs in recent years, a reduction in power consumption of SRAMs are also in progress. As a method of reducing power consumption of an SRAM, there is a method of using a high-voltage power supply only for SRAM cells and a part of word line control circuit and using a low-voltage power supply for other circuits. A high power reduction effect can be obtained by this method because the voltage of a voltage power supply for bit lines can be reduced.
For example, Japanese Patent Application Laid-Open No. H9-282890 discloses a method of boosting a first voltage applied to an SRAM to a higher second voltage to actuate a memory cell array and a decoder with the first voltage and actuate a sense amplifier with the second voltage.
However, in the method of reducing the voltage of a voltage power supply for bit lines to realize a reduction in power consumption of an SRAM, because a pre-charge power supply has to be shared with a sense amplifier connected to the bit lines, a voltage power supply for the sense amplifier is also reduced in voltage. Therefore, sensing speed of the sense amplifier substantially drops to cause a reduction in speed of the SRAM.
In the method disclosed in Japanese Patent Application Laid-Open No. H9-282890, because a high-voltage power supply is used for the sense amplifier, a voltage power supply for bit lines connected to the sense amplifier is also increased in voltage to cause an increase in power consumption.